Hardware Acceleration of Singular Value Decomposition with the One-Sided Jacobi Algorithm

Author(s):

William Diehl

Abstract:

Computationally intensive singular value decompositions (SVDs) are required for several current and emerging information fields such as unsupervised learning and signal processing. There are several well-known algorithms for performing SVD and its closely related eigenspace decomposition; however, these algorithms generally grow at a complexity of O[n_³] with an increasing matrix size. In contrast, hardware implementations can exploit parallel computation to achieve orders of magnitude speed ups, i.e., O[n]. In this research, we demonstrate a hardware implementation of a widely used SVD algorithm: the one-sided Jacobi (OSJ) SVD. To preserve maximum internal precision and stability, we implement the OSJ SVD entirely in single-precision floating point. We conduct simulations in Python and C-based hardware and software codesign to investigate architectural choices such as dividers and implementation of complex rotation computations. We implement the OSJ–SVD hardware accelerator using a Xilinx Zynq UltraScale+ FPGA and prototyped in the ZCU208 evaluation board for 8 × 8 matrices. Our implementation achieves a 133-times speed up over an equivalent CPU OSJ SVD in the Zynq MPSoC with less than 1% difference in the largest 50% of eigenvalues between hardware accelerator and C implementation. The lessons we learned from this work position us to improve future implementations and directly couple an SVD accelerator to high-speed streaming applications such as ML and wideband RF signal processing.